Adaptive electropolishing using thickness measurement and removal of barrier and sacrificial layers

ABSTRACT

A metal layer formed on a semiconductor wafer is adaptively electropolished. A portion of the metal layer is electropolished, where portions of the metal layer are electropolished separately. Before electropolishing the portion, a thickness measurement of the portion of the metal layer to be electropolished is determined. The amount that the portion is to be electropolished is adjusted based on the thickness measurement. A metal layer formed on a semiconductor wafer is polished, where the metal layer is formed on a barrier layer, which is formed on a dielectric layer having a recessed area and a non-recessed area, and where the metal layer covers the recessed area and the non-recessed areas of the dielectric layer. The metal layer is polished to remove, the metal layer covering the non-recessed area. The metal layer in the recessed area is polished to a height below the non-recessed area, where the height is equal to or greater than a thickness of the barrier layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of earlier filed provisionalapplication U.S. Ser. No. 60/397,941, entitled METHOD FORELECTROPOLISHING METAL FILM ON SUBSTRATE, filed on Jul. 22, 2002, andU.S. Ser. No. 60/403,996, entitled METHODS FOR BARRIER AND SACRIFICIALLAYER REMOVAL, filed on Aug. 17, 2002, the entire contents of which areincorporated herein by reference.

BACKGROUND

1. Field of the Invention

The present application relates to electropolishing a metal film formedon a substrate, and more particularly to adaptively electropolishing ametal film formed on a semiconductor wafer using the thicknessmeasurements of the metal film. The present application also relates toremoval of barrier and sacrificial layers during polishing and plasmaetching processes.

2. Related Art

Semiconductor devices are manufactured or fabricated on semiconductorwafers using a number of different processing steps to create transistorand interconnection elements. To form transistor and/or interconnectionelements, the semiconductor wafer may undergo, for example, masking,etching, and deposition processes to form the desired electroniccircuitry of the semiconductor devices. In particular, in a damasceneprocess, multiple masking and etching steps can be performed to form apattern of recessed areas in a dielectric layer on a semiconductor waferthat serve as trenches and vias for the interconnections. A depositionprocess may then be performed to deposit a metal layer over thesemiconductor wafer thereby depositing metal both in the trenches andvias and also on the non-recessed areas of the semiconductor wafer. Toisolate the interconnections, such as patterned trenches and vias, themetal layer deposited on the non-recessed areas of the semiconductorwafer is removed.

However, if excessive or insufficient amounts of the metal layer areremoved, then the transistor and/or interconnection element maymalfunction. For example, if an excessive amount of metal is removedfrom the trenches that form the interconnections, then theinterconnections may not be able to properly transmit electricalsignals.

Additionally, the use of dielectric materials having low dielectricconstants (low-k dielectrics) has been introduced as a way to reduce thesignal delays at the interconnections of conductors. However, becauselow-c dielectric materials having porous microstructures, they also havelow mechanical integrity and thermal conductivity as compared to otherdielectric materials. Consequently, low-k dielectric materials typicallycannot sustain the stress and pressure applied to them during aconventional damascene process.

In a conventional damascene process, a barrier layer may be formed overthe metal or low-k dielectric materials. Because the barrier layer istypically formed by hard and chemically inert material, such as TaN, Ta,Ti, and TiN, the barrier layer is difficult to remove using CMP orelectropolishing, except by using higher pad pressure during CMP or highvoltage using electropolishing. In the case of CMP, higher pad pressurecan increase surface defect density, or even delaminate the low-kdielectric. In the case of electropolishing, higher polishing voltagecan remove excessive amounts of the metal, which can increase the lineresistance. When conventional plasma etching is used to remove thebarrier layer, over-etching is necessary in order to make sure that allof the barrier layer on non-recessed areas is removed. However, theover-etching can cause voids when the next cover layer is deposited.Metal atoms can diffuse out from the void and can even diffuse to thedevice gate region, which can make the semiconductor device malfunction.

SUMMARY

In one exemplary embodiment, a metal layer formed on a semiconductorwafer is adaptively electropolished. A portion of the metal layer iselectropolished, where portions of the metal layer are electropolishedseparately. Before electropolishing the portion, a thickness measurementof the portion of the metal layer to be electropolished is determined.The amount that the portion is to be electropolished is adjusted basedon the thickness measurement.

In another exemplary embodiment, a metal layer formed on a semiconductorwafer is polished, where the metal layer is formed on a barrier layer,which is formed on a dielectric layer having a recessed area and anon-recessed area, and where the metal layer covers the recessed areaand the non-recessed areas of the dielectric layer. The metal layer ispolished to remove the metal layer covering the non-recessed area. Themetal layer in the recessed area is polished to a height below thenon-recessed area, where the height is equal to or greater than athickness of the barrier layer.

DESCRIPTION OF DRAWING FIGURES

The present invention can be best understood by reference to thefollowing description taken in conjunction with the accompanying drawingfigures, in which like parts may be referred to by like numerals:

FIG. 1 depicts an exemplary electropolishing module;

FIG. 2A depicts an exemplary thickness mapping of a metal layer formedon a semiconductor wafer;

FIGS. 2B and 2C depict a portion of the mapping depicted in FIG. 2A;

FIG. 3 depicts various mapping schemes;

FIG. 4 depicts an exemplary control system connected to a plurality ofexemplary electropolishing modules;

FIG. 5 depicts an exemplary control system connected to a plurality ofexemplary electropolishing modules through a plurality of subsystems;

FIGS. 6A to 6D depict an exemplary damascene process;

FIGS. 7A to 7D depict another exemplary damascene process;

FIGS. 8A to 8D depict still another exemplary damascene process; and

FIGS. 9A to 9D depict yet another exemplary damascene process.

DETAILED DESCRIPTION

The following description sets forth numerous specific configurations,parameters, and the like. It should be recognized, however, that suchdescription is not intended as a limitation on the scope of the presentinvention, but is instead provided as a description of exemplaryembodiments.

I. Adaptive Electropolishing

As described earlier, in forming transistor and interconnection elementson a semiconductor wafer, metal is deposited and removed from thesemiconductor wafer. More specifically, a layer of metal (i.e., a metallayer) is formed on the semiconductor wafer using a deposition process,such as chemical vapor deposition (CVD), physical vapor deposition(PVD), atomic layer deposition (ALD), electroplating, electrolessplating, and the like. The metal layer is then removed using an etchingor polishing process, such as chemical mechanical polishing (CMP),electropolishing, and the like.

With reference to FIG. 1, in one exemplary embodiment, anelectropolishing module 100 can be used to remove/polish a metal layerformed on semiconductor wafer 102. In the present exemplary embodiment,wafer 102 is held by wafer chuck 112, which rotates wafer 102 aboutangle theta and translates wafer 102 laterally, such as in thex-direction as depicted in FIG. 1. While wafer 102 is rotated andtranslated by wafer chuck 112, an electrolyte is applied to the metallayer formed on wafer 102 through nozzle 108 and/or nozzle 110. Asdepicted in FIG. 1, nozzle 108 can be configured to apply a narrowerstream of electrolyte than nozzle 110. As such, nozzle 108 can be usedfor a more precise polishing than nozzle 110. For example, nozzle 110can be used for an initial rough polishing, where an initial amount ofthe metal layer is polished from the surface of wafer 102, then nozzle108 can be used for a subsequent finer polishing, where the metal layeris polished more uniformly than during the initial rough polishing. Inthe present exemplary embodiment, an end-point detector 106 can be usedto measure the thickness of the metal layer on the surface of wafer 102.In FIG. 1, end point detector 106, nozzle 108, and nozzle 110 aredepicted as being disposed adjacent to each other on a nozzle plate 104.It should be recognized, however, that end point detector 106, nozzle108, and nozzle 110 can be arranged in various configurations andmounted in a variety of manners. Additionally, it should be recognizedthat any number of nozzles, including one nozzle, can be used toelectropolish the metal layer on wafer 102. Furthermore, it should berecognized that end point detector 106, nozzle 108 and/or nozzle 110 cantranslate either instead of or in addition to translating wafer 102using wafer chuck 112.

For a more detailed description of an exemplary electropolishing processand system, see U.S. Pat. No. 6,394,152 B1, entitled METHODS ANDAPPARATUS FOR ELECTROPOLISHING METAL INTERCONNECTIONS ON SEMICONDUCTORDEVICES, filed on Jul. 2, 1999; U.S. Pat. No. 6,248,222 B 1, entitledMETHODS AND APPARATUS FOR HOLDING AND POSITIONING SEMICONDUCTORWORKPIECES DURING ELECTROPOLISHING AND/OR ELECTROPLATING OF THEWORKPIECES; and U.S. Provisional Application Ser. No. 60/372,566,entitled METHOD AND APPARATUS FOR ELECTROPOLISHING AND/ORELECTROPLATING, filed on Apr. 14, 2002, the entire contents of which areincorporated herein by reference. For a more detailed description of anexemplary end point detector, see U.S. Pat. No. 6,447,668, entitledMETHOD AND APPARATUS FOR END-POINT DETECTION, filed on May 12, 2000, theentire content of which is incorporated herein by reference.

In the present embodiment, wafers are generally processed using a recipethat includes various processing parameters, such as liquid flow rate,current or voltage set-point, center-to-edge distance, initialrotational speed, polishing duration, center polishing rotational speed,nozzle type, current or voltage table, bulk ratio table for constantcurrent, repetition setting, and the like. Because wafers processedusing the same deposition process will generally have similar metallayer thickness profiles, the wafers can be initially polished usingsimilar polishing recipes.

However, as described above, in polishing the metal layer formed on awafer, polishing too much or too little of the metal layer can result inthe semiconductor device malfunctioning. Thus, in the present exemplaryembodiment, the thickness of the metal layer on a wafer is used toadaptively electropolish the metal layer. More particularly, beforeelectropolishing a portion of the metal layer formed on the wafer, thethickness of the portion to be electropolished is determined, and theamount that the portion is electropolished is adjusted based on thedetermined thickness.

For example, a control system 114 can be connected to wafer chuck 112and nozzle 108 and nozzle 110. Based on the position of wafer chuck 112,control system 114 can determine the location of the portion of themetal layer on wafer 102 to be electropolished. Control system 114determines the thickness of the portion of the metal layer to beelectropolished, and adjusts the amount that the portion iselectropolished by nozzle 108 and/or nozzle 110.

In one exemplary embodiment, before wafer 102 is processed in polishingmodule 100, a substrate thickness metrology tool 116 is used to measureand map the thickness of the metal layer on wafer 102. With reference toFIG. 2A, metrology tool 116 (FIG. 1) can provide thickness measurementsat various locations 202 on wafer 102. Note that locations 202 can bemapped using various coordinate systems. For example, as depicted inFIG. 2A, a simple x and y coordinate axes can be used. Alternatively,radius and the angle theta, corresponding to the angle of rotation ofwafer 102, can be used. Control system 114 (FIG. 1) can then use themapping of the thickness of the metal layer on wafer 102 to obtain thethickness of a portion of the metal layer prior to electropolishing theportion.

As depicted in FIG. 2A, the mapping of the thickness of the metal layeron wafer 102 may include gaps, meaning locations where the thickness ofthe metal layer is not known. More particularly, as depicted in FIG. 2A,the rotation and translation of wafer 102 results in the stream ofelectrolyte applied by nozzle 108 (FIG. 1) and/or nozzle 110 (FIG. 1) ina spiral path 204. As also depicted in FIG. 2A, the stream ofelectrolyte may be applied in a location 206, where the thickness of themetal layer is not known. Thus, in the present exemplary embodiment,thickness measurements from two or more locations 202, where thethickness of the metal layer is known are used to determine thethickness of the metal layer in location 206.

For example, as depicted in FIG. 2B, the thickness of the metal layer atlocation 206 is determined based on the thickness of the metal layer atlocations 202A, 202B, 202C, and 202D. Note that in accordance with the xand y coordinate system used in FIG. 2A, location 206 corresponds toposition (x, y), and locations 202A, 202B, 202C, and 202D correspond topositions (x_(i), y_(j+1)), (x_(i+1), y_(j+1)), (x_(i+1), y_(j)), and(x_(i), y_(j)), respectively. FIG. 2C depicts the variation in thethickness of the metal layer in a perspective view.

In the present example, assume that the thickness of the metal layer atlocation 206 is characterized by the following expression:T=Ax+By+Cxy+D  (1)Additionally, the thickness T_(ij) at (x_(i),y_(j)), thickness T_(ij+1)at (x_(i),y_(j+1)), and T_(i+1,j) at (x_(i+1), yj), and thicknessT_(i+1,j+1) at (x_(i+1),y_(j+1)) are assumed to be characterized by thefollowing expressions:T _(i,j) =Ax _(i) +By _(j) +Cx _(i) y _(i) +D  (2)T _(i,j+1) =Ax _(i) +By _(j+1) +Cx _(i) y _(j+1) +D  (3)T _(i+1,j) =Ax _(i+1) +By _(j) +Cx _(i+1) y _(j) +D  (4)T _(i+1,j+1) =Ax _(i+1) +By _(j+1) +C  (5)The values of A, B, C, and D can then be obtained by solving equations(2)-(5) in the following manner:C=(T _(i,j) −T _(i,j+1) −T _(i+1,j) +T _(i+1,j+1))/[(x _(i) −x_(i+1))*(y _(j) −y _(j+1))]B=(T _(i,j) −T _(i,j+1))/(y _(j) −y _(j+1))−x _(i) *DA=(T _(i,j) −T _(i+1,j))/(x _(i) −x _(i+1))−y _(j) *DD=T _(i,j) −x _(i) *B−y _(i)*[(T _(i,j) −T _(i,j+1))/(y _(j) −y _(j+1))]

It should be recognized that any number of locations 202, where thethickness of the metal layer is known, can be used to determine thethickness of the metal layer at location 206. For example, for a moreaccurate interpolation than that described above, the thickness of themetal layer at location 206 can be assumed to be characterized by thefollowing expression:T=Ax ² +By ² +Cxy+Dx+Ey+F  (6)The Thickness T at (x, y) can be interpolated using 6 locations closestto location 206, and the constants A, B, C, D, E, and F can be obtainedby solving 6 equations in the same manner as the constants A, B, C, andD were solved above when using 4 locations.

With reference again to FIG. 1, in the present exemplary embodiment,thickness measurements of the metal layer on wafer 102 can be obtainedusing end point detector 106. More particularly, wafer 102 can berotated and translated adjacent end point detector 106 in the samemanner as when wafer 102 is electropolished using nozzle 108 and/ornozzle 110. Thus, thickness measurements of the metal layer on wafer 102can be obtained along the same path 204 (FIG. 2) as would be followedwhen the metal layer is electropolished-using nozzles 108 and/or nozzle110.

For example, when end point detector 106 is an optical sensor,reflectivity of the surface of wafer 102 adjacent to end point detector106 can be recorded as wafer 102 is rotated and translated. Thethickness of the metal layer at a location, such as location 206 (FIG.2) can then be calculated using the following formula:T(x, y)=P(T)*R(x, y)  (7)where R(x, y) is the reflectivity of metal film at location 206 (FIG. 2)measured by end point detector 106, and P(T) is the conversion factor ofreflectivity to thickness, which itself is a function of thickness. P(T)can be determined by using a set of metal layers with differentthickness that are known, then correlating the known thicknesses to thereflectivity of the metal layers. The determined conversion factor,P(T), can then be used to determine the thickness that corresponds to areflectivity of a metal layer with unknown thickness.

Alternatively, the known thicknesses and the correspondingreflectivities can be stored, such as in a look-up table, in a computer,such as in control system 114. For example, the look-up table caninclude a thickness matrix stored in computer memory as follows:T_(1,1) T_(1,2) T_(1,3) . . . T_(1,m)T_(2,1) T_(2,2) T_(2,3) . . . T_(2,m)T_(3,1) T_(3,2) T_(3,3) . . . T_(3,m)T_(n,1) T_(n,2) T_(n,3) . . . T_(n,m)with each thickness in the thickness matrix having a correspondingreflectivity.

After measuring the reflectivity at location 206 (FIG. 2) using endpoint detector 106, control system 114 can determine the thickness T(x,y), such as by using a conversion factor, P(T) or a look-up table. Themetal layer can then be electropolished using the thickness measurement.The process can be repeated until the reflectivity recorded by end-pointdetector 106 is within a pre-set range. It should be noted that thepre-set range of reflectivity can depend on various factors, such asmetal pattern density, over-polishing range, and the like. In general,the less the patterned density, the lower pre-set of reflectivity. Also,the preset reflectivity can vary based on pattern density. The presetreflectivity can be calculated based on pattern density of mask ormeasured by one polished wafer with minimum metal recess. For a moredetailed described of calculating the preset reflectivity, see U.S. Pat.No. 6,447,668, entitled METHOD AND APPARATUS FOR END-POINT DETECTION,filed on May 12, 2000, the entire content of which is incorporatedherein by reference.

It should be recognized that end-point detector 106 can be various typesof sensors. For example, end-point detector 106 can be an eddy-currentsensor. Thus, end-point detector 106 is used to measure eddy currentsrather than reflectivity, and the thickness of the metal layer isdetermined based on the measured eddy currents rather than the measuredreflectivity.

While thickness measurements obtained using end point detector 106 canfollow the same path as the path followed when the metal layer iselectropolished, gaps may still exist in the thickness measurements. Forexample, the thickness measurements can be taken at intervals ratherthan continuously in order to increase throughput When gaps exist in thethickness measurements, the interpolation process described above can beused to obtain thickness measurements in locations where thicknessmeasurements are not known.

Additionally, in the present exemplary embodiment, a grid-by-gridimaging can be used to map and locate any position on a wafer. Moreparticularly, the surface of a wafer can be mapped into pixelpartitions, where each pixel partition corresponds to a field that canbe measured using end point detector 106 (FIG. 1). FIG. 3 depictsvarious exemplary pixel partitions. End point detector 106 (FIG. 1) canmeasure the reflectivity for a given position (x, y), or a pixel,preferably with a size of 2.5 mm by 2.5 mm, starting from center of awafer to the edge of a wafer or from the edge to the center. End-pointdetector 106 (FIG. 1) can move from one pixel at a time and record thereflectivity data for each pixel until all the pixels are recorded, suchas up to 11,494 pixels (i.e., πR²/(2.5)²) for a 200 mm wafer.

In the present exemplary embodiment, an initial rough electropolishingis performed using an initial thickness measurement obtained from asubstrate thickness metrology tool prior to electropolishing the wafer.After the initial rough electropolishing is completed, an intermediatethickness measurement of the metal layer is obtained, for example, usingan end point detector. The metal layer is then electropolished againusing the intermediate thickness measurement The initial roughelectropolishing can be completed when the thickness of the metal layeris below a threshold thickness, such as about 1000 Å. It should berecognized, however, that the metal layer can be electropolished basedon the initial thickness measurement and without the intermediatethickness measurement. Alternatively, the metal layer can beelectropolished based on the thickness measurement obtained, forexample, using an end-point detector without the initial thicknessmeasurement.

As described above, in the present exemplary embodiment, the amount thata portion of the metal layer is electropolished is adjusted based on thethickness measurement of the portion. The amount that the portion iselectropolished can be adjusted by varying the current and/or voltageapplied to the stream of electrolyte applied to the portion. Forexample, the applied polishing current can be determined based on thethickness as follows:I=kT(x, y)  (7)where k is the factor related to polishing rate. In addition to varyingthe current and/or voltage applied to the stream of electrolyte, itshould be recognized that the amount of time the stream of electrolyteis applied to the portion (i.e., polishing duration) can be adjustedbased on the thickness measurement of the portion. Moreover, anycombination of current, voltage, and polishing duration can be adjustedbased on the thickness measurement of the portion.

Thus, with reference to FIG. 1, in the present exemplary embodiment,control system 114 determines the thickness measurement of a portion ofthe metal layer to be electropolished, then adjusts the amount that theportion is electropolished based on the determined thicknessmeasurement. As described above, control system 114 can adjust thecurrent and/or voltage applied to the stream of electrolyte applied bynozzle 108 and/or nozzle 110. Control system 114 can also adjust thepolishing duration by controlling the rate of rotation and/ortranslation of wafer chuck 112.

In the present exemplary embodiment, the amount of delay from the timewhen control system 114 determines the adjustment to make and when theadjustment is implemented (i.e., Δt) is used as an offset time inadvance of when control system 114 determines the adjustments, to bemade for a portion of the metal layer control system 114 before thatportion is electropolished. For example, when the current applied to thestream of electrolyte applied by nozzle 108 is to be adjusted for aportion of the metal layer, control system 114 determines the current tobe applied in advance by at least the offset time (i.e., Δt) of nozzle108 reaching the portion to be electropolished.

With reference now to FIG. 4, control system 114 can be connected to aplurality of electropolishing modules 100 (e.g., processing chamber 1(PC1), PC2, and PC3). As depicted in FIG. 4, control system 114 executesthe process control for each electropolishing module 100. For example,for each electropolishing module 100, control system 114 executes thepolishing recipe, records thickness measurements (e.g., reflectivitydata), processes the thickness measurements and updates the metal filmthickness profile, adjusts the electropolishing (e.g., adjusting thecurrent or voltage applied to the stream of electrolyte applied by anozzle), and repeats the polishing recipe for each wafer to beelectropolished. Control system 114 also performs various additionaltasks, such as graphical user interface, wafer handling, alarmmanagement, and the like.

However, the processing and computing load required of control system114 can reduce response time for tasks, such as read-outs, electricaloutput, and mechanical motion. Increasing the number of loads thatcontrol system 114 is required to handle can reduce the completion timefor each load. Thus, in the present exemplary embodiment, control system114 includes a plurality of distributed subsystems, where task-orientedfunctions are off loaded to individual subsystems, such as a motionserver block controller.

More particularly, with reference now to FIG. 5, one subsystem 502 isdedicated to one electropolishing module 100 (e.g., PC1, PC2, or PC3).The distributive subsystem depicted in FIG. 5 reduces the time lag thatcan be associated with a central system depicted in FIG. 4. In theexemplary embodiment depicted in FIG. 5, a PC based control system 114receives and sends data to each subsystems 502 using a device-to-devicetransmission media 504, such as RS485, DeviceNet, and the like.

For example, each subsystem 502 can perform the same set of tasks foreach electropolishing module 100. As depicted in FIG. 5, one subsystem502 can be dedicated to operate the chuck, motor drives, nozzles, andend-point detector, and to process the data for digital IO and analog IOfor PC1. Simultaneously, the other subsystems 502 can be dedicated totheir respective electropolishing modules 100. For example, anothersubsystem 502 can be dedicated to operate the chuck, motor drives,nozzles, and end-point detector, and to process the data for digital IOand analog IO for PC2.

Under the distributive arrangement, each subsystem 500 can exert betterand finer control in both mechanical and electrical performance (i.e.,to record both rotational angle and location of the wafer with remainingmetal layer and to control nozzle functions based on the reflectivityrecorded for the given location in 4 milliseconds or better). With eachsubsystem 502 having increased processing capacity, the presentexemplary embodiment can add or extrapolate other values or tables inthe recipe based on the reflectivity data to achieve finer control ofthe polishing.

Moreover, as the result of distributing processing requirement of thewafer electropolishing distributed to subsystems 502, control system 114and subsystems 502 can have more available processing power to operateor perform other tasks. In particular, additional tools and/orapplications can be added to the polishing process without diminishingthe speed or practicality of such tool configurations. For example, aninline metrology tool can be added to measure the profile of each waferbefore the wafer is loaded to an electropolishing module. The inlinemetrology tool can measure the thickness of the metal layer on a waferfor a subsystem 502 or control system 114 to determine the requiredcurrent output to achieve a more flat uniform metal surface. Subsystem502 or control system 114 can then generate a new table with data, suchas the distance versus current rate times user defined set-points.

II. Removing Barrier and Sacrificial Layers

FIGS. 6A-6D depict an exemplary damascene process that can be used toform interconnections in a semiconductor device. In particular, withreference to FIG. 6A, the semiconductor device can include a dielectricmaterial 608 having recessed area 606 and non-recessed area 610, whererecessed area 606 can be a structure such as a wide trench, a largerectangular structure, and the like. A barrier layer 604 can bedeposited on dielectric material 608 by any convenient depositionmethod, such as CVD, PVD, ALD, and the like, such that barrier layer 604covers both recessed area 606 and non-recessed area 610. For a moredetailed description of dielectric material and barrier layer, see U.S.patent application Ser. No. 10/380,848, entitled METHOD FOR INTEGRATINGCOPPER WITH ULTRA-LOW K DIELECTRICS, filed on Mar. 14, 2003; U.S. patentapplication Ser. No. 10/108,614, entitled ELECTROPOLISHING METAL LAYERSON WAFERS HAVING TRENCHES OR VIAS WITH DUMMY STRUCTURES, filed on Mar.27, 2002, which claims priority of an earlier filed provisionalapplication U.S. Ser. No. 60/286,273, of the same title, filed on Apr.24, 2001. The entire content of these applications are incorporatedherein by reference.

In the present exemplary process, with reference to FIG. 6B, a metallayer 612 can be deposited on barrier layer 604 by any convenientmethod, such as PVD, CVD, ALD, electroplating electroless plating, andthe like. Next, with reference to FIG. 6C, metal layer 612 is polishedback using CMP, electropolishing, and the like, such that metal layer612 is removed from non-recessed area 610, while metal layer 612 is leftin recessed area 606. Metal layer 612 can include various electricallyconductive materials, such as copper, aluminum, nickel, chromium, zinc,cadmium, silver, gold, rhodium, palladium, platinum, tin, lead, iron,indium, super-conductor materials, and the like. Metal layer 612 canalso include an alloy of any of the various electrically conductivematerials, or compound of superconductor. Preferably, metal layer 612includes copper and its alloys.

Now, with reference to FIG. 6D, after removing metal layer 612 fromnon-recessed area 610, barrier layer 604 can be removed fromnon-recessed area 610 by any convenient method such as wet etching, drychemical etching, dry plasma etching, and the like. In order to entirelyremove barrier layer 604 on non-recessed area 610, over-etching isrequired. However, as depicted in FIG. 6D, over-etching can produce anotch 614. When the next cover layer, such as SiN and the like, aredeposited in the present exemplary process, notch 614 can become a void,which can lead to metal bleeding. The bled metal can diffuse throughdielectric material 608 and down to the device gate region, causing thesemiconductor device to malfunction.

As shown in FIGS. 7A-7D, a combination of overpolish using electropolishand plasma etching can be used to address this problem. In the presentexemplary process, with reference to FIG. 7A, metal layer 612 inrecessed area 606 is overpolished using electropolishing, wet etching,and the like, so that there exists h micron in height between the top ofbarrier layer 604 and the surface of metal layer 612 within recessedarea 606, where the height h is equal to or greater than the thicknessof barrier layer 604. It should be recognized that electropolishing canhave better control and therefore cause less process problems whentrying to overpolish metal layer 612 in recessed area 606 as comparedwith wet etching method. For a description of electropolishing, see U.S.Pat. No. 6,395,152, entitled METHODS AND APPARATUS FOR ELECTROPOLISHINGMETAL INTERCONNECTIONS ON SEMICONDUCTOR DEVICES, filed on Jul. 2, 1999,which is incorporated in its entirety herein by reference.

Next, with reference to FIG. 7B, additives, such as CF₄/O₂, SF₆/O₂, andthe like, are added to the etching gases, Ta, C, and F, to form aresidue 702 on barrier layer 604 and metal layer 612 within recessedarea 606. As shown in FIG. 7C, when barrier layer 604 is being etchedaway, the presence of residue 702 can prevent barrier layer 604 betweendielectric material 608 and metal layer 612 in recessed area 606 frombeing over-etched.

The following table, Table 1, provides an exemplary range of parametersthat can be employed in a plasma dry etch process to remove barrierlayer 604: TABLE 1 Plasma Power: 500 to 2000 W Vacuum: 30 to 100 mTorrTemperature of wafer: approximately 20° C. Gas and flow rate: SF₆ = 50sccm, CF₄ = 50 sccm, or O₂ = 10 sccm Gas pressure: 0.1 to 50 mTorrRemoval rate of TaN: 250 nm/min Removal rate of TiN: 300 nm/min Removalrate of SiO₂: 200˜400 nm/min

These parameters result in a removal rate of TaN and TiN, two possiblebarrier layer 604 materials, close to that of SiO₂, a possibledielectric material 608 material. The selectivity can be selected inthis manner to reduce etching or damaging the underlying dielectricmaterial 608 during the removal of barrier layer 604. It should benoted, however, that other selectivity can be obtained by varying theparameters.

Now with reference to FIG. 7D, a portion of recessed area 606 andnon-recessed area 610 of about Δd can be removed by using plasma etchingprocess, or dry chemical cleaning, or any other convenient process. Theetch rate of barrier layer 604 should be set equal or lower than that ofdielectric material 608 in order to make sure that barrier layer 604 isequal or higher than dielectric material 608 in height. Therefore, novoids will be formed when the next top layer is deposited.

In FIGS. 8A to 8D, another exemplary process is shown. The exemplaryprocess shown in FIGS. 8A to 8D is similar in many respects to theprocess shown in FIGS. 7A to 7D, except that a hard mask layer 802 isdeposited on dielectric material 608 before the wafer undergoes etchingand deposition processes that form recessed areas such as 606. As shown,hard mask layer 802 can prevent etching of dielectric material 608underneath of bard mask layer 802 during barrier removal processes andtherefore avoid the performance degradation of dielectrics, especiallylow-k dielectrics. Recess h should be less than the sum of thickness ofbarrier layer 604 and the thickness of hard mask 802.

In FIGS. 9A to 9B, another exemplary process is shown. Similar to FIGS.8A to 8D, the exemplary process shown in FIGS. 9A to 9D is similar inmany respects to the process shown in FIGS. 7A to 7D, except that inaddition to hard mask layer 802, a sacrificial layer 902 is deposited ontop of hard mask layer 802. While hard mask layer 802 has lower removalrate than that of barrier layer 604, in this exemplary process,sacrificial layer 902 with a removal rate equal or greater than that ofbarrier layer 604 is used.

In both FIGS. 8A to 8D and FIGS. 9A to 9D, hard mask layer 802 can beselected from SiN, SiC, SiO₂, SiON, diamond film, and the like.Sacrificial layer 902 can be selected from SiN, SiO₂, SiON, and thelike.

Although exemplary embodiments have been described, variousmodifications can be made without departing from the spirit and/or scopeof the present invention. Therefore, the present invention should not beconstrued as being limited to the specific forms shown in the drawingsand described above.

1. A method of adaptively electropolishing a metal layer formed on asemiconductor wafer, the method comprising: electropolishing a portionof the metal layer, wherein portions of the metal layer areelectropolished separately; before electropolishing the portion,determining a thickness measurement of the portion of the metal layer tobe electropolished; and adjusting an amount that the portion is to beelectropolished based on the thickness measurement.
 2. The method ofclaim 1, wherein electropolishing a portion of the metal layercomprises: applying a stream of electrolyte to the portion of the metallayer through a nozzle adjacent to the portion of the metal layer. 3.The method of claim 2, wherein the wafer is held, rotated, andtranslated using a wafer chuck while the nozzle is held stationaryadjacent to the metal layer.
 4. The method of claim 2, wherein the waferis held and rotated using a wafer chuck while the nozzle is translatedadjacent to the metal layer.
 5. The method of claim 2, wherein adjustingan amount that the portion is to be electropolished comprises: adjustinga polishing current or voltage applied to the stream of electrolyte. 6.The method of claim 2, wherein adjusting an amount that the portion isto be electropolished comprises: adjusting a polishing duration of theportion.
 7. The method of claim 1, wherein determining a thicknessmeasurement comprises: obtaining a map of the thickness measurement ofthe metal layer determined using a thickness metrology tool.
 8. Themethod of claim 7, wherein determining a thickness measurement furthercomprises: measuring thickness measurements of the metal layer using anend-point detector; and wherein adjusting an amount that the portion isto be electropolished comprises: adjusting the amount that the portionis to be electropolished during an initial polishing using the map ofthe thickness measurement of the metal layer determined using thethickness metrology tool; and adjusting the amount that the portion isto be electropolished during a subsequent polishing using the thicknessmeasurement measured using the end point detector.
 9. The method ofclaim 7, further comprising: interpolating a thickness measurement of aportion of the metal layer not having a thickness measurement on the mapbased on a plurality of thickness measurements of portions of the metallayer having thickness measurements on the map.
 10. The method of claim1, wherein determining a thickness measurement comprises: measuringthickness measurements of the metal layer using an end point detectoradjacent to the metal layer.
 11. The method of claim 10, wherein thewafer is held, rotated, and translated using a wafer chuck while the endpoint detector is held stationary adjacent to the metal layer.
 12. Themethod of claim 10, wherein the thickness measurements are mapped usinga plurality of pixel partitions, wherein a pixel position corresponds toa field that can be measured using the end point detector.
 13. Themethod of claim 10, further comprising: determining an end to polishingthe portion based on a metal density of pattern on the wafer.
 14. Themethod of claim 10, wherein the end point detector is an optical sensor.15. The method of claim 10, wherein the end point detector is an eddycurrent sensor.
 16. A system for adaptively electropolishing a metallayer formed on a semiconductor wafer, the method comprising: anelectropolishing module configured to electropolish portions of themetal layer separately; and a control system configured to: determine athickness measurement of a portion of the metal layer before the portionis electropolished, and adjust an amount that the portion iselectropolished based on the thickness measurement.
 17. The system ofclaim 16, wherein the electropolishing module comprises: a nozzleconfigured to apply a stream of electrolyte to the portion of the metallayer.
 18. The system of claim 17, further comprising: a wafer chuckconfigured to hold, rotate, and translate the wafer while the nozzle isheld stationary adjacent to the nozzle.
 19. The system of claim 17,wherein the nozzle is configured to translate, and further comprising: awafer chuck configured to hold and rotate the wafer.
 20. The system ofclaim 17, wherein the control system is configured to adjust a polishingcurrent or voltage applied to the stream of electrolyte or adjust apolishing duration of the portion.
 21. The system of claim 16, whereinthe control system is configured to determine the adjustment to theamount that the portion is electropolished in advance ofelectropolishing the portion by an offset time.
 22. The system of claim16, further comprising: a thickness metrology tool, wherein the controlsystem obtains a map of the thickness measurement of the metal layerfrom the thickness metrology tool.
 23. The system of claim 16, whereinthe electropolishing module comprises: an end point detector configuredto measure the thickness of the metal layer.
 24. The system of claim 23,wherein the electropolishing module further comprises: a wafer chuckconfigured to hold, rotate, and translate the wafer while the end pointdetector is held stationary adjacent to the metal layer.
 25. The systemof claim 23, wherein the electropolishing module further comprises: awafer chuck configured to hold and rotate the wafer while the end pointdetector is translated.
 26. The system of claim 23, wherein the endpoint detector is an optical sensor or an eddy current sensor.
 27. Thesystem of claim 23, wherein the end-point detector is configured todetermine an end to polishing the portion based on a metal density ofpattern on the wafer.
 28. The system of claim 16, wherein theelectropolishing module comprises: a first processing chamber; a firstsubsystem configured to control the first process chamber; a secondprocessing chamber; and a second subsystem configured to control thesecond process chamber, wherein the control system is connected to thefirst and second subsystems.
 29. A method of polishing a metal layerformed on a semiconductor wafer, wherein the metal layer is formed on abarrier layer, which is formed on a dielectric layer having a recessedarea and a non-recessed area, and wherein the metal layer covers therecessed area and the non-recessed areas of the dielectric layer, themethod comprising: polishing the metal layer to remove the metal layercovering the non-recessed area; and polishing the metal layer in therecessed area to a height below the non-recessed area, wherein theheight is equal to or greater than a thickness of the barrier layer. 30.The method of claim 29, wherein polishing the metal layer compriseselectropolishing the metal layer.
 31. The method of claim 30, whereinelectropolishing the metal layer comprises: applying a stream ofelectrolyte to a portion of the metal layer through a nozzle adjacent tothe portion of the metal layer.
 32. The method of claim 31, furthercomprising: holding, rotating, and translating the wafer using a waferchuck while the nozzle is held stationary.
 33. The method of claim 31,further comprising: holding and rotating the wafer using a wafer chuckwhile the nozzle is translated.
 34. The method of claim 29, furthercomprising: after polishing the metal layer, removing the barrier layerfrom the non-recessed area using plasma etching.
 35. The method of claim34, wherein plasma etching comprises using an etching gas, and whereinan additive is added to the etching gas to form a residue on the metallayer and the barrier layer in the recessed area.
 36. The method ofclaim 34, further comprising: removing a portion of the recessed andnon-recessed area using plasma etching, wherein the etch rate of thebarrier layer within the recessed area is equal to or higher than theetch rate of the dielectric layer.
 37. The method of claim 29, wherein ahard mask layer is disposed between the dielectric layer and barrierlayer, and wherein the height is less than the sum of the thickness ofthe barrier layer and a thickness of the hard mask layer.
 38. The methodof claim 37, wherein a sacrificial layer is disposed between the hardmask layer and barrier layer, wherein the hard mask layer has a lowerremoval rate than the barrier layer and the sacrificial layer has aremoval rate equal to or greater than the barrier layer.
 39. The methodof claim 29, wherein the dielectric layer includes a low-k dielectricmaterial, and the metal layer includes copper.
 40. A layer of asemiconductor wafer comprising: a dielectric layer having recessed andnon-recessed area; a barrier layer deposited above the dielectric layer;and a metal layer deposited on the barrier layer, wherein the metallayer is removed from the non-recessed area of the dielectric layer andpolished in the recessed area to a height below the non-recessed area,wherein the height is equal to or greater than a thickness of thebarrier layer.
 41. The layer of a semiconductor wafer of claim 40,further comprising: a hard mask layer disposed between the dielectriclayer and barrier layer, wherein the height is less than the sum of thethickness of the barrier layer and a thickness of the hard mask layer.42. The layer of a semiconductor wafer of claim 41, further comprising:a sacrificial layer disposed between the hard mask layer and barrierlayer, wherein the hard mask layer has a lower removal rate than thebarrier layer and the sacrificial layer has a removal rate equal to orgreater than the barrier layer.
 43. The layer of semiconductor wafer ofclaim 40, wherein the dielectric layer includes a low-k dielectricmaterial, and the metal layer includes copper.